The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices relating to read-modify-write memory and multiple read-or-write banks.
A variety of memory applications, such as SRAM, DRAM, thin capacitively coupled thyristor applications and others, include a read-or-write bank having a set of memory cells for read-or-write data access. In a minimally prescribed amount of time (hereinafter a xe2x80x9cbank cyclexe2x80x9d), data is read from or written to a subset of those cells (hereinafter a xe2x80x9cwordxe2x80x9d). The read-or-write access rate of such a memory is the frequency at which read or write operations may be performed, and is comparable to the inverse of the bank cycle time, with the bank cycle time increasing as the capacity of the bank increases.
An array of read-or-write banks can be combined in a read-or-write memory to attain a large memory capacity while keeping the bank cycle time of the memory to a minimum. In such a memory, a xe2x80x9cmemory cyclexe2x80x9d is the time in which a word can be read from or written to the read-or-write memory via access to an appropriate read-or-write bank. Thus, the memory cycle time of the memory is typically comparable to or greater than the bank cycle time. The read-or-write access rate of such a memory array is the frequency at which read or write operations can be performed, and is comparable to the inverse of the memory cycle time.
Read-modify-write data access is another type of data access that is desirable in a variety of memory applications. In such applications, one or more words of data are read from memory, modified and written back into the memory. For brevity, further discussion is limited to single words with the understanding that this following discussion of example embodiments can be extended to multiple words of data
In some instances, read-or-write memory has been utilized to support read-modify-write operations. For example, one memory cycle can be used to read a word that is subsequently modified over a period of zero or more memory cycles. The word is then written back to the memory in another memory cycle. The modification of the data does not actually use the memory: therefore, other memory accesses may be interleaved during the period of time during which the data is being modified. Thus, this read-or-write memory has a read-modify-write access using two memory operations, with two corresponding memory cycles, from the read-or-write memory. Therefore, the read-modify-write access rate of the memory (e.g., the frequency with which read-modify-write operations may be performed) has been one half the read-or-write access rate.
The present invention is directed to the above-discussed subject matter and others relating to the devices where minimum access rate is a concern. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a read-modify-write memory includes a read-or-write bank, and the read-modify-write access rate of the memory is about equal to the read-or-write access rate of the read-or-write bank. In one implementation, the memory includes one or more read-or-write banks coupled with a single read-modify-write bank, hereinafter a xe2x80x9ccache.xe2x80x9d At most one access to any given read-or-write bank is generated for each read-modify-write access to the memory. In this manner, the memory supports a read-modify-write access rate that is about equal to the slowest of the cache and the read-or-write bank access rates.
In a more particular example embodiment of the present invention, read access is effected from a read-modify-write memory having at least one read-or-write bank and a cache using one access to a read-or-write bank for each read access to the memory. An incoming address request is received and a word from a read-or-write bank corresponding to the incoming address is read. A word is also read from a row of a cache corresponding to the row of the read-or-write bank, along with a cache tag that indicates which read-or-write bank""s word is contained in the cache. In response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, data (e.g., one or more words) is returned from the cache for the read access. When the tag indicates that the cache does not contain the word of the read-or-write bank corresponding to the incoming address, data is returned from the read-or-write bank for the read access.
In another example embodiment of the present invention, a write access is effected from a read-modify-write memory having at least one read-or-write bank and a cache using one access to the read-or-write bank for each write access to the memory. An incoming address request is received and a cache tag that indicates which read-or-write bank""s word is contained in the cache is read. In response to the tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address, data (e.g., one or more words) is written to the cache for the write access. When the tag indicates that the cache does not contain the word of the read-or-write bank corresponding to the incoming address, data is written to the read-or-write bank for the write access.
In still another example embodiment of the present invention, a read-modify-write access is effected from a read-modify-write memory having at least one read-or-write bank and a cache using one access to the read-or-write bank for each write access to the memory. An incoming address request is received, a word is read from a read-or-write bank corresponding to the incoming address and from a row of the cache corresponding to a row of the read-or-write bank at the incoming address, and a cache tag that indicates which read-or-write bank""s word is contained in the cache is also read. In response to the cache tag indicating that the cache contains the word of the read-or-write bank corresponding to the incoming address,.the word read from the cache is modified and written back to the cache. When the tag indicates that the cache does not contain the word of the read-or-write bank corresponding to the incoming address, the word read from the cache is written to the read-or-write bank corresponding to the tag, the word read from the read-or-write bank corresponding to the incoming address is modified and written to the cache. In addition, the cache tag is updated to indicate that the word in the cache now contains the word from the read-or-write bank corresponding to the incoming address.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.